PIC18LF66K80-I/PT【PDF 41/351 页】MCU PIC ECAN 64KB FLASH 64TQFP

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2010-2012 Microchip Technology Inc.

DS39977F-page 135

PIC18F66K80 FAMILY

7.5

Writing to Flash Program Memory

The programming blocks are 32 words or 64 bytes.

Word or byte programming is not supported.

Table writes are used internally to load the holding regis-

ters needed to program the Flash memory. There are

64 holding registers for programming by the table writes.

Since the Table Latch (TABLAT) is only a single byte, the

TBLWT

instruction may need to be executed 64 times for

each programming operation. All of the table write oper-

ations will essentially be short writes because only the

holding registers are written. At the end of updating the

64 or 128 holding registers, the EECON1 register must

be written to in order to start the programming operation

with a long write.

The long write is necessary for programming the inter-

nal Flash. Instruction execution is halted while in a long

write cycle. The long write is terminated by the internal

programming timer.

The EEPROM on-chip timer controls the write time.

The write/erase voltages are generated by an on-chip

charge pump, rated to operate over the voltage range

of the device.

FIGURE 7-5:

TABLE WRITES TO FLASH PROGRAM MEMORY

7.5.1

FLASH PROGRAM MEMORY WRITE

SEQUENCE

The sequence of events for programming an internal

program memory location should be:

Read the 64 bytes into RAM.

Update the data values in RAM as necessary.

Load the Table Pointer register with the address

being erased.

Execute the row erase procedure.

Load the Table Pointer register with the address

of the first byte being written.

Write the 64 bytes into the holding registers with

auto-increment.

Set the EECON1 register for the write operation:

Set the EEPGD bit to point to program memory

Clear the CFGS bit to access program memory

Set the WREN to enable byte writes

Disable the interrupts.

Write 55h to EECON2.

10. Write 0AAh to EECON2.

11. Set the WR bit. This will begin the write cycle.

The CPU will stall for the duration of the write for

TIW (see Parameter D133A).

12. Re-enable the interrupts.

13. Verify the memory (table read).

An example of the required code is shown in

Example 7-3 on the following page.

Note:

The default value of the holding registers on

device Resets and after write operations is

FFh. A write of FFh to a holding register

does not modify that byte. This means that

individual bytes of program memory may

be modified, provided that the change does

not attempt to change any bit from a ‘0’ to a

‘1’. When modifying individual bytes, it is

not necessary to load all 64 holding

registers

before

executing

write

operation.

TABLAT

TBLPTR = xxxx3F

TBLPTR = xxxxx1

TBLPTR = xxxxx0

Write Register

TBLPTR = xxxxx2

Program Memory

Holding Register

Note:

Before setting the WR bit, the Table

Pointer address needs to be within the

intended address range of the 64 bytes in

the holding register.

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